71. Grams. S. Lin and you will J. B. Kuo, “Fringing-Caused Slim-Channel-Impression (FINCE) Related Capacitance Choices away from Nanometer FD SOI NMOS Products Playing with Mesa-Isolation Via three dimensional Simulator” , EDSM , Taiwan ,
72. J. B. Kuo, “Advancement out-of Bootstrap Techniques in Reasonable-Current CMOS Digital VLSI Circuits to have SOC Software” , IWSOC , Banff, Canada ,
P. Yang, “Entrance Misalignment Feeling Related Capacitance Choices out of an effective 100nm DG FD SOI NMOS Product that have n+/p+ Poly Greatest/Bottom Gate” , ICSICT , Beijing, China
73. Grams. Y. Liu, N. C. Wang and you may J. B. Kuo, “Energy-Successful CMOS Higher-Weight Driver Routine with the Subservient Adiabatic/Bootstrap (CAB) Way of Lowest-Stamina TFT-Liquid crystal display Program Software” , ISCAS , Kobe, Japan ,
74. Y. S. Lin, C. H. Lin, J. B. Kuo and K. W. Su, “CGS Capacitance Occurrence regarding 100nm FD SOI CMOS Gadgets having HfO2 High-k Gate Dielectric Offered Straight and you can Fringing Displacement Effects” , HKEDSSC , Hong kong ,
75. J. B. KUo, C. H. Hsu and you may C. P. Yang, “Gate-Misalignment Relevant Capacitance Conclusion off a good 100nm DG SOI MOS Gadgets that have Letter+/p+ Top/Base Entrance” , HKEDSSC , Hong kong ,
76. Grams. Y. Liu, N. C. Wang and you can J. B. Kuo, “Energy-Efficient CMOS High-Load Rider Circuit on the Complementary Adiabatic/Bootstrap (CAB) Technique for Lower-Electricity TFT-Liquid crystal display System Software” , ISCAS , Kobe, Japan ,
77. H. P. Chen and J. B. Kuo, “A beneficial 0.8V CMOS TSPC Adiabatic DCVS Reasoning Circuit to the Bootstrap Strategy to have Reduced-Power VLSI” , ICECS , Israel ,
B. Kuo, “A book 0
80. J. B. Kuo and you will H. P. Chen, “A decreased-Voltage CMOS Stream Rider on the Adiabatic and you will Bootstrap Approaches for Low-Stamina System Apps” , MWSCAS , Hiroshima, Japan ,
83. M. T. Lin, Age. C. Sunrays, and you will J. B. Kuo, “Asymmetric Gate Misalignment Influence on Subthreshold Attributes DG SOI NMOS Devices Considering Fringing Electric Field effect” , Electron Gizmos and you can Procedure Symposium ,
84. J. B. Kuo, E. C. Sun, and you may M. T. Lin, “Research out of Door Misalignment Affect new Endurance Current off Twice-Gate (DG) Ultrathin FD SOI NMOS Gadgets Playing with a concise Design Offered Fringing Electric Field effect” , IEEE Electron Equipment to own Microwave oven and you will Optoelectronic Programs ,
86. E. Shen and J. 8V BP-DTMOS Content Addressable Thoughts Cellphone Routine Produced from SOI-DTMOS Process” , IEEE Meeting into the Electron Gadgets and you can Solid-state Circuits , Hong kong ,
87. P. C. Chen and J. B. Kuo, “ic Reason Routine Playing with an immediate Bootstrap (DB) Technique for Lowest-voltage CMOS VLSI” , Global Symposium toward Circuits and you can Options ,
89. J. B. Kuo and S. C. Lin, “Compact Dysfunction Model to own PD SOI NMOS Gadgets Given BJT/MOS Effect Ionization getting Spice Circuits Simulator” , IEDMS , Taipei ,
90. J. B. Kuo and you can S. C. Lin, “Lightweight LDD/FD SOI CMOS Device Design Given Energy Transport and you will Mind Temperatures getting Liven Routine Simulator” , IEDMS , Taipei ,
91. S. C. Lin and you can J. B. Kuo, “Fringing-Created Hindrance Lowering (FIBL) Ramifications of 100nm FD SOI NMOS Products with high Permittivity Gate Dielectrics and you can LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg ,
92. J. B. Kuo and S. C. Lin, “The Fringing Electronic Field effect to your Short-Station Feeling Threshold Current off FD SOI NMOS Devices with LDD/Sidewall Oxide Spacer Framework” , Hong-kong Electron Equipment Appointment ,
93. C. L bir posta sipariЕџi gelinin maliyeti ne kadardД±r. Yang and you will J. B. Kuo, “High-Temperature Quasi-Saturation Make of Highest-Voltage DMOS Energy Equipment” , Hong kong Electron Gizmos Conference ,
94. E. Shen and J. B. Kuo, “0.8V CMOS Stuff-Addressable-Memories (CAM) Mobile Ciurcuit with a fast Mark-Examine Possibilities Having fun with Vast majority PMOS Active-Threshold (BP-DTMOS) Strategy According to Simple CMOS Technical to own Lowest-Voltage VLSI Options” , Internationally Symposium into Circuits and Assistance (ISCAS) Proceedings , Arizona ,